#ifndef __DT_BINDINGS_CV186X_DMAMAP_H__
#define __DT_BINDINGS_CV186X_DMAMAP_H__

#define CVI_I2S0_RX     0
#define CVI_I2S0_TX     1
#define CVI_I2S1_RX     2
#define CVI_I2S1_TX     3
#define CVI_I2S2_RX     4
#define CVI_I2S2_TX     5
#define CVI_I2S3_RX     6
#define CVI_I2S3_TX     7
#define CVI_I2S4_RX     8
#define CVI_I2S4_TX     9
#define CVI_I2S5_RX     10
#define CVI_I2S5_TX     11
#define CVI_I2S_dw_RX   12
#define CVI_I2S_dw_TX   13
#define CVI_UART0_RX    14
#define CVI_UART0_TX    15
#define CVI_UART1_RX    16
#define CVI_UART1_TX    17
#define CVI_UART2_RX    18
#define CVI_UART2_TX    19
#define CVI_UART3_RX    20
#define CVI_UART3_TX    21
#define CVI_UART4_RX    22
#define CVI_UART4_TX    23
#define CVI_UART5_RX    24
#define CVI_UART5_TX    25
#define CVI_UART6_RX    26
#define CVI_UART6_TX    27
#define CVI_UART7_RX    28
#define CVI_UART7_TX    29
#define CVI_SPI0_RX     30
#define CVI_SPI0_TX     31
#define CVI_SPI1_RX     32
#define CVI_SPI1_TX     33
#define CVI_SPI2_RX     34
#define CVI_SPI2_TX     35
#define CVI_SPI3_RX     36
#define CVI_SPI3_TX     37
#define CVI_I2C0_RX     38
#define CVI_I2C0_TX     39
#define CVI_I2C1_RX     40
#define CVI_I2C1_TX     41
#define CVI_I2C2_RX     42
#define CVI_I2C2_TX     43
#define CVI_I2C3_RX     44
#define CVI_I2C3_TX     45
#define CVI_I2C4_RX     46
#define CVI_I2C4_TX     47
#define CVI_I2C5_RX     48
#define CVI_I2C5_TX     49
#define CVI_I2C6_RX     50
#define CVI_I2C6_TX     51
#define CVI_I2C7_RX     52
#define CVI_I2C7_TX     53
#define CVI_I2C8_RX     54
#define CVI_I2C8_TX     55
#define CVI_I2C9_RX     56
#define CVI_I2C9_TX     57
#define CVI_TDM0_RX     58
#define CVI_TDM0_TX     59
#define CVI_TDM1_RX     60
#define CVI_AUDSRC      61
#define CVI_SPI_NAND    62
#define CVI_SPI_NOR     63

#endif
